Search - cpu verilog

[Other] Verilog

Description: 程序员利用一种由专家设计的既可以被人理解，也可以被计算机解释的语言来表示算法问题的求解过程。这种语言就是编程语言。由它所表达的算法问题的求解过程就是程序。我们已经熟悉通过编写程序来解决计算问题， C、Pascal、Fortran、Basic 或汇编语言语言是几种常用的编程语言。如果我们只研究算法，只在通用的计算机上运行程序或利用通用的CPU 来设计专用的微处理器嵌入系统，掌握上述语言就足够了。如果还需要设计和制造能进行快速计算的硬线逻辑专用电路，我们必须学习数字电路的基本知识和硬件描述语言。因为现代复杂数字逻辑系统的设计都是借助于EDA 工具完成的，无论电路系统的仿真和综合都需要掌握硬件描述语言。在本书中我们将要比较详细地介绍Verilog 硬件描述语言。-Programmers to take advantage of a design by the experts can either be understood algorithmic problem solving process can also be explained by the computer language to represent. This language is a programming language. By it expressed algorithmic problem solving process is the program. We are already familiar with to solve computational problems by writing programs in C, Pascal, Fortran, Basic or assembly language language several common programming languages. If we only study the algorithm, running on a general purpose computer program to design a dedicated microprocessor embedded systems or the use of general-purpose CPU master the above language is sufficient. If you need to design and manufacturing for quick calculation of the hard-wired logic circuit, we must learn the basic knowledge of digital circuit hardware description language. Because the design of the modern complex digital logic systems are accomplished by means of EDA tools, regardless of the circuit system simulation a
Platform: | Size: 1346560 | Author: exia_dl | Hits:

[Software Engineering] CPU-implementation-in-verilog

Description: 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
Platform: | Size: 412672 | Author: yuxin tan | Hits:

[Other] CPU

Description: 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
Platform: | Size: 292864 | Author: 邹楠 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
Platform: | Size: 3288064 | Author: | Hits:

[VHDL-FPGA-Verilog] System-Verilog-and-HDL-skills

Description: 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UMTExNzExOTgw/videos and tells about some of FPGA logic design techniques
Platform: | Size: 3183616 | Author: 易瑜 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用system verilog写的一个arm处理器原代码。-Write an ARM processor system verilog source code.
Platform: | Size: 3225600 | Author: 张力 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
Platform: | Size: 4337664 | Author: 刘栋 | Hits:

[Software Engineering] lab-1-ALU-design-with-Verilog-HDL

Description: cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Platform: | Size: 19456 | Author: 张明明 | Hits:

[Software Engineering] lab-4-cpu-design-with-Verilog-HDL

Description: 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
Platform: | Size: 22528 | Author: 张明明 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
Platform: | Size: 518144 | Author: yu | Hits:

[Other] pipelined-CPU

Description: verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
Platform: | Size: 7625728 | Author: 黄晓颖 | Hits:

[VHDL-FPGA-Verilog] avr_core_latest.tar

Description: avr cpu verilog 源码实现，欢迎下载使用-avr cpu verilog source implementations are welcome to download
Platform: | Size: 193536 | Author: dodoo123 | Hits:

[File Format] CPU

Description: 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
Platform: | Size: 1844224 | Author: xiaokai | Hits:

[VHDL-FPGA-Verilog] singleCPU

Description: 用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.
Platform: | Size: 7304192 | Author: 孔晗聪 | Hits:

[VHDL-FPGA-Verilog] Verilog-language--de-CPU

Description: 基于verilog语言的FPGA开发，平台在QuartusII上，对SDRAM的读写-Verilog language based FPGA development platform on QuartusII, the SDRAM read and write
Platform: | Size: 41984 | Author: 宋雪涛 | Hits:

[Other] 88RISC-CPU

Description: cpu设计能在quartus上运行用verilog语言-a cpu program use verilog on quartus
Platform: | Size: 4400128 | Author: 倪歌 | Hits:

[Other] DLX_verilog

Description: DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
Platform: | Size: 3072 | Author: 石建刚 | Hits:

[SCM] cpu

Description: Verilog代码，支持IO，中断的cpu实现。-Verilog code, support IO, interrupt cpu implementation.
Platform: | Size: 12288 | Author: lslifediyi | Hits:

[VHDL-FPGA-Verilog] cpu

Description: verilog 8 bit cpu working condition but need minor modification
Platform: | Size: 10240 | Author: shobhit | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
Platform: | Size: 12288 | Author: 胡森 | Hits:

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[Other] Verilog

[Software Engineering] CPU-implementation-in-verilog

[Other] CPU

[VHDL-FPGA-Verilog] RISC-CPU

[VHDL-FPGA-Verilog] System-Verilog-and-HDL-skills

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] RISC-CPU

[Software Engineering] lab-1-ALU-design-with-Verilog-HDL

[Software Engineering] lab-4-cpu-design-with-Verilog-HDL

[VHDL-FPGA-Verilog] CPU

[Other] pipelined-CPU

[VHDL-FPGA-Verilog] avr_core_latest.tar

[File Format] CPU

[VHDL-FPGA-Verilog] singleCPU

[VHDL-FPGA-Verilog] Verilog-language--de-CPU

[Other] 88RISC-CPU

[Other] DLX_verilog

[SCM] cpu

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] CPU

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